The present invention generally relates to flip-flop circuits, and more particularly to a flip-flop circuit such as a master slave type flip-flop circuit having a reduced number of transistor gates.
Flip-flop circuits are one of basic circuits most frequently used in digital circuits. Hence, in order to further improve the integration density of integrated circuits, it is necessary to further reduce the number of transistor gates of the flip-flop circuit.
A master slave type flip-flop circuit is made up of a master circuit and a slave circuit. The master circuit latches the input data during a first half of 1 clock period, and the slave circuit latches and outputs during the second half of the 1 clock period the input data that was latched by the master circuit.
FIG. 1 shows the circuit construction of an example of a conventional master slave type flip-flop circuit. In FIG. 1, a master circuit includes transmission gates 1 and 2, and CMOS inverters 5 and 6. On the other hand, a slave circuit includes transmission gates 3 and 4, and CMOS inverters 7, 8 and 9. Each of the transmission gates 1 through 4 are made up of a PMOS gate and a NMOS gate which are connected in parallel. A clock signal CK and an inverted clock signal/CK are applied to each of the transmission gates 1 through 4.
In FIG. 1, when the clock signal CK has a low level, the transmission gate 1 turns ON and the input data is input to the CMOS inverter 5. In this state, the transmission gates 2 and 3 are OFF, and the transmission gate 4 is ON.
Next, when the clock signal CK undergoes a transition to a high level, the transmission gate 2 turns ON. As a result, the CMOS inverter 6 inverts the data output from the CMOS inverter 5 and inputs the inverted data to the CMOS inverter 5, so that the CMOS inverter 5 latches the input data. On the other hand, the transmission gate 3 turns ON, and the input data latched by the CMOS inverter 5 is input to the CMOS inverter 7. In this state, the transmission gates 1 and 4 are OFF.
Then, when the clock signal CK undergoes a transition to the low level, the transmission gate 4 turns ON. As a result, the CMOS inverter 8 inverts the data output from the CMOS inverter 7 and inputs the inverted data to the CMOS inverter 7, so that the CMOS inverter 7 latches the input data. Responsive to this latch process, the CMOS inverter 7 outputs the input data to the outside, and the CMOS inverter 9 outputs an inverted value of the input data to the outside.
Therefore, according to the conventional master slave type flip-flop circuit, the master circuit latches the input data during the first half of 1 clock period, and the slave circuit latches and outputs during the second half of the 1 clock period the input data that was latched in the master circuit.
On the other hand, a toggle type flip-flop circuit has the function of inverting the output for every incoming clock signal, and is used in a counter circuit or the like. When forming the toggle type flip-flop circuit shown in FIG. 2 in the form of an integrated circuit using the conventional master slave type flip-flop circuit described above, the data output from the CMOS inverter 9 is input to a data terminal D to which the input data is supplied.
However, according to the conventional master slave type flip-flop circuit, a transmission gate is used at each of the four switching parts, and there was a problem in that the number of gates becomes large. In addition, there was another problem in that two kinds of clock signals (CK and/CK) are required to switch the transmission gates.
In other words, each transmission gate is made up of a parallel connection of the PMOS gate which turns ON when a low-level clock signal is input to the gate and turns OFF when a high-level clock signal is input to the gate, and the NMOS gate which turns ON when a high-level clock signal is input to the gate and turns OFF when a low-level clock signal is input to the gate. Hence, the ON state of the transmission gate is realized by turning ON both the PMOS gate and the NMOS gate, and the OFF state of the transmission gate is realized by turning OFF both the PMOS gate and the NMOS gate. For this reason, there were problems not only in that the number of gates becomes large, but also in that the two kinds of clock signals (CK and /CK) are required to switch the transmission gates.